Silicon carbide semiconductor device and method for manufacturing the same

专利摘要:
SUMMARY A semiconductor device comprises a silicon carbide semiconductor substrate (5), a transistor formed in a cell region (R1) of the semiconductor substrate (5), and a voltage breakdown resistant structure formed in a region (R2) surrounding an outer periphery of the cell region (R1). The semiconductor substrate (5) comprises a substrate (1) of first conductivity type, an operating layer (2) of first conductivity type on the substrate (1) of first conductivity type, a layer (3) of second conductivity types on the operating layer (2), and a layer (4 ) of the first conductivity type on the layer (3) of second conductivity types. The stress breakthrough resistant structure comprises a first recess (17) which surrounds the outer periphery of the cell region (R1) and when the operating layer (2), a trench (13, 45) arranged at a side surface of the recess (17) on an inner periphery of the recess (17). ), and a buried layer (15, 46) of other conductivity types buried in the ditch (13, 45) to provide the side surface of the first recess (17).
公开号:SE537601C2
申请号:SE1450265
申请日:2012-08-08
公开日:2015-07-14
发明作者:Yuichi Takeuchi；Naohiro Suzuki
申请人:Denso Corp；
IPC主号:

专利说明:

[1] This application is based on Japanese Patent Application No. 2011-174774 filed August 10, 2011, the contents of which are incorporated herein by reference.
[2] The present description relates to a silicon carbide semiconductor device (hereinafter referred to as SIC) having an external voltage breakdown resistant region around a transistor cell region where JFET cells, MOSFET cells, or the like are formed, and also relates to a method of making the same.
[3] A SiC semiconductor device comprising a JFET having a ditch structure has been known (refer to, for example, patent document 1). In the SiC semiconductor device an N-type operating layer, a P + type first gate region, and an N + type source region formed in turn on an N + type SiC substrate, a ditch penetrating these is formed and then an N --type channel layer and a P + type other street region an formed in the ditch. A gate voltage applied to a gate electrode electrically connected to the other gate region is controlled so that a drain current can flow between a source electrode electrically connected to the N + type source region and a drain electrode electrically connected to the N + type SiC substrate. It can be considered that when an external voltage breakthrough resistant structure is formed in such a SiC semiconductor device as described above, a mesa structure is formed by forming a recess in an external region around a transistor cell region where a JFET is formed, and when a P type RESURF layer or a P-type protective ring layer is formed at a branch of the recess. Although the Ptype RESURF layer or the P-type protective ring layer is formed by selective ion implantation of P-type impurities after the recess is formed, the following problem occurs. This problem is described with reference to FIG. 18A and 18B.
[5] FIG. 18A and 18B are cross-sectional diagrams illustrating a method of forming a P-type RESURF layer as an external voltage breakdown resistant structure. As shown in the drawings, a JFET base structure is formed by forming an N-type operating layer J2, a P + type first gate region J3, and an N + type sourcing region J4 is in turn formed on an N + type SIC substrate J1, forming a ditch J5 which penetrates these, and then form an N-type channel layer J6 and a P + type second street region J7 is formed in the ditch J5. Then a recess J8 is formed which is deeper than the N + source region J3 by selective etching by means of a mask. Then a recess J9 is formed which is deeper than the first street region J3 by selective etching by means of another mask. Thereafter, a P-type RESURF layer J10 is formed by selective ion implantation of P-type 10 impurities.
[6] At this time, it can be considered that the P-type RESURF layer J10 can be formed by normal ion implantation in which ion implantation of P-type contaminants is performed in a direction normal to a substrate surface as shown in FIG. 18A or by an inclined ion implant in which a P-type impurity ion implant is performed in a direction inclined at a predetermined angle with respect to the direction normal to the substrate as shown in FIG. 18B.
[7] However, when ion implantation is performed in the direction normal to the substrate surface, the P-type RESURF layer J10 is not formed at a side surface of the recess J9 and at a corner portion defining a boundary between the side surface and a bottom surface of the recess J9. Since the first gate region J3 and the P-type RESURF layer J10 are separated from each other on the side surface of the recess J9, a pull-through break voltage at the time of OFF is greatly reduced to, for example, 400V or less. That is to say, since the P-type RESURF layer J10 does not exist at the corner portion of the recess J9, concentration of electrical fait occurs at this portion so that the pull-through breakdown voltage can be reduced.
[8] On the other hand, when inclined ion implantation is performed, the P-type RESRUF layer is formed at the side surface and the corner portion of the recess J9. Therefore, the breakthrough voltage at the time kw AV Okas can be, for example, around 1300V. However, since there is a need to perform inclined ion implantation in four directions in turn around the transistor cell region where the JFET is formed, an ion implantation procedure becomes complicated and time consuming. As a result, the manufacturing cost of the device increases.
[9] In the above description, the P-type RESURF layer is formed as an external voltage breakthrough resistant structure. However, this is not limited to the P-type RESURF layer J10, and the same applies when a P-type protective ring is formed. 2 PRIOR ART PATENT DOCUMENT Patent document 1: JP-A-2005-150352 SUMMARY OF THE INVENTION
[11] In view of the above, it is an object of the present disclosure to provide a SiC semiconductor having an external voltage breakdown resistant structure, which is formed without inclined ion implantation and surrounds an outer periphery of a transistor cell region where JFET or the like is formed, to provide a high torque breakdown voltage.
[12] According to a first aspect of the present description, an outer voltage breakthrough resistant structure formed in an outer voltage breakthrough resistant structural region comprises first recesses, a first trench and an electrically folded relieving structure. The first ditch surrounds an outer periphery of a transistor cell region and is deeper than a first conductivity layer and a second conductivity layer to reach an operating layer. The first ditch is arranged at a side surface of the first recess on an inner periphery of the first recess and surrounds the outer periphery of the transistor cell region. The electrically fold-relieving structure has after buried layers of other conductivity types. The buried layer of other conductivity types is buried in the first trench and provides the side surface of the first recess. Since the side surface of the first recess is provided by the buried layer of other conductivity types to provide the electrically field relieving structure, the concentration of electric field at the horn is relieved which defines a boundary between the side surface and a bottom surface. Therefore, a breakthrough position is moved to the operating layer on the bottom surface of the first recess. Thus, the electric field is relieved so that a drain breakdown voltage can be improved.
[15] As described above, when the second recess is formed, it is preferred that the first recess is arranged longer boil from the transistor cell region than the second recess.
[16] According to a third aspect of the present description, another layer of second conductivity types is formed on an adjacent side of a bottom surface of the second recess to the first recess and on an adjacent side of the bottom surface of the first recess to the second recess. The second conductivity type layer is joined to the buried layer of other conductivity types to form a RESURF layer of other conductivity types which provides the electrically faulty structure.
[17] Since the second conductivity impact layer on the adjacent side of the bottom surface of the second recess to the first recess and the second conductivity impact layer on the adjacent surface of the bottom surface of the first recess to the second recess are continuously joined together to form P type RESURF layer 20, an ideal traction breakdown voltage at the time of OFF can be set.
[18] According to a fourth aspect of the present description, multiple first ditches are arranged out of the boundary between the first recess and the second recess, and the buried layer of second conductivity types is formed in each of the first ditches to form a protective ring structure which provides the electrically fell relieving structure. As described above, the protective ring structure is formed by the buried layer of second conductivity types in each of the first ditches. Even when such a protective ring structure is formed, the buried layer of other conductivity types can be arranged at the side surface of the first recess by using the first ditch and the buried layer of other conductivity types. Thus, the same benefits as the third aspect can be obtained.
[20] According to a fifth aspect of the present description, multiple first ditches are provided food from the boundary between the first recess and the second recess, and the buried layer of second conductivity types is formed in each of the first ditches to form a protective ring structure which provides the electrically folded relief structure.
[21] In this way, the protective ring structure can be formed within the boundary between the first recess and the second recess. In this case, when the buried layer of second conductivity type is formed on a buried layer of first conductivity type in the first ditch, the protective ring structure formed in the second recess has the first ditch, the buried layer of first conductivity type, and the buried layers of second conductivity type. . Thus, the second conductivity layer is arranged between the first ditches. Not only the buried layer of other conductivity types, but also the layer of other conductivity types, functions as the protective ring structure, and a distance between them becomes the same as a thickness of the buried layer of first conductivity type only. Accordingly, the electric field in the protective ring structure is reduced so that a stable drainage breakdown voltage can be easily maintained.
[22] According to a sixth aspect of the present description, the first ditches are arranged in descending order of their width in an outward direction of the transistor cell region.
[23] As described above, the first ditches may be arranged in descending order of their width in the outward direction of the transistor cell region. In this case, when a first or a second buried conductivity layer having a contaminant concentration lower than that of the first buried conductivity layer or the second buried conductivity layer is formed before the buried layer of other conductivity types is formed in each of the first ditches, the depths of the other buried the conductivity layers gradually decrease. In such a structure, the electric field is further relieved at the time of AV. Thus, compared to when the other buried conductivity layers have the same depth, even when the size of the external voltage breakthrough resistant structural region is small, the same or higher tensile breakdown voltage can be stated.
[24] According to a seventh aspect of the present disclosure, a JFET is formed in the transistor cell region. The JFET includes a first gate region, a source region, a second ditch, a channel layer of first conductivity type, a second gate region of second conductivity type, a source electrode and a drain electrode. The first street region is the supply of the layer of other conductivity types. The source region is the supply of the layer of first conductivity type. The second ditch reaches the operating layer by penetrating the first conductivity layer and the second conductivity layer. The channel layer is formed by epitaxial growth on an inner rock of the second ditch. The second street region is formed on the channel layer. The source electrode is electrically connected to the first conductivity layer. The drain electrode is electrically connected to a substrate of the first conductivity type. A source-to-drain current is controlled by controlling a potential of at least one of the first gate region and the second gate region. As described above, the present description can be applied to a SIC semiconductor device having a JFET in the transistor cell region. In this case, the first ditch and the buried layer of second conductivity types can be formed by using methods in which the second ditch, the channel layer and the second street region are formed. In this way, since after the manufacturing process is commonly used, the electrically relieved structure can be formed without an increase in the manufacturing process.
[26] According to a ninth aspect of the present description, a MOSFET is formed in the transistor cell region. The MOSFET includes a base region, a source region, a gate insulating layer, a gate electrode, a source electrode, a drain electrode, a second trench, and a deep layer of other conductivity types. The base region is the supply of the layer of other conductivity types. The source region is the supply of the layer of first conductivity type. The gate insulating layer is formed on a surface of the base region between the source region and the operating layer. The gate electrode is formed on a surface of the gate insulating layer. The source electrode is electrically connected to the layer of first conductivity type. The drain electrode is electrically connected to a substrate of the first conductivity type. The second ditch reaches the operating layer by penetrating the first conductivity layer and the second conductivity layer. The deep layer of other conductivity types is buried in the second ditch.
[27] As described above, the present description can be applied to a SiC semiconductor device having a MOSFET in the transistor cell region. In this case, the first ditch and the buried layer of other conductivity types can be formed by using methods in which the second ditch and the deep layer are formed. In this way, since a manufacturing method is commonly used, the electrically low-relief structure can be formed without an increase in the manufacturing method.
[29] As described above, the MOSFET formed in the transistor cell region may have a ditch gate structure. In this case, the second ditch in which the deep layer is buried is deeper than the next ditch of the ditch street structure. Thus, the electric field provided to the gate insulating layer is reduced at the time of AV so that a breakthrough of the gate insulating layer can be prevented.
[30] In the second to eleventh aspects described above, the present description is defined as a device. Alternatively, the present description may be defined as a manufacturing process. ToIfte to the twenty-second aspect corresponds to processes for the manufacture of SiC semiconductor devices of the first to the eleventh aspect.
[31] According to a twelfth aspect of the present description, a step of manufacturing a step of manufacturing the semiconductor substrate comprises a step of forming a first trench in the outer voltage breakdown resistant structural region so that the first trench surrounds the outer periphery of the transistor cell region, a step of forming a buried layer of other conductivity types in the first ditch, and a step of forming after the first recess which is deeper than the layer of first conductivity layer and the layer of other conductivity types and when the operating layer is such that the first recess surrounds the outer periphery of the transistor cell region. In the step of forming the first recess, the first ditch is arranged at a side surface of the first recess on an inner periphery of the first recess so that the side surface of the first recess is provided by the buried layer of other conductivity types to form an electrically relieving load. structure having the buried layer of other conductivity types. By this method, the SiC semiconductor device according to the first aspect can be manufactured.
[32] According to a thirteenth aspect of the present description, the manufacturing method further comprises a step of forming a second recess deeper than a thickness of the layer of first conductivity type such that the second recess surrounds the outer periphery of the transistor cell region. In the step of forming the first recess, the first ditch is arranged at a boundary between the first recess and the second recess so that the side surface of the first recess at the boundary between the first recess and the second recess is the supply of the buried layer of second conductivity type. to form the electric field relieving structure having the buried layer of other conductivity types. By this method, the SiC semiconductor device according to the second aspect can be manufactured.
[33] According to a fourteenth aspect of the present description, the manufacturing method further comprises a step of forming a second conductivity layer on an adjacent side of a bottom surface of the second recess to the first recess and on an adjacent side of a bottom surface of the first recess to the first recess. the second recess in such a way that the second conductivity layer is connected to the buried layer of second conductivity types to form a RESURF layer of other conductivity types which provides the electrically field relieving structure. The step of forming the second conductivity layer follows the step of forming the first recess and the step of forming the second recess and comprises a step of forming a mask on a surface of the substrate and a step of performing ion implantation of contaminants of other conductivity types. in a direction normal to the substrate by applying the mask.
[34] As described above, the layer of other conductivity types is formed by performing ion implantation of contaminants of other conductivity types in a direction normal to the substrate. By this method, a SiC semiconductor device according to the third aspect can be manufactured. According to a fifteenth aspect of the present description, in the step of forming the first ditch, multiple first ditches are formed such that the first ditches are arranged from the boundary between the first recess and the second recess, and in the step of forming the buried layer of other conductivity types, the buried layer is formed of other conductivity types in each of the first ditches to form a protective ring structure which provides the electrically field relieving structure. By this method, the SiC semiconductor device according to the fourth aspect can be manufactured.
[36] According to a sixteenth aspect of the present description, in the step of forming the first ditch, multiple first ditches are formed in such a way that the first ditches are arranging food from the boundary between the first recess and the second recess, and in the step of forming the buried layer of other conductivity types, the buried layer of second conductivity types is formed in each of the first ditches to form a protective ring structure which provides the electrically field relieving structure. By this method, the SiC semiconductor device according to the fifth aspect can be manufactured. According to a seventeenth aspect of the present description, in the step of forming the first ditch, the first ditches are formed so that the first ditches are arranged in descending order of their width in an outward direction of the transistor cell region. By this method, the SiC semiconductor device according to the sixth aspect can be manufactured.
[38] According to an eighteenth aspect of the present description, the manufacturing method further comprises the step of forming a JFET in the transistor cell region. The JFET has a first gate region provided by the layer of second conductivity types and a source region provided by the layer of first conductivity types. The step of forming the JFET comprises a step of forming a second trench which reaches the operating shift by penetrating the first conductivity layer and the second conductivity layer, a step of forming a channel layer of first conductivity by epitaxial growth on an inner rock of the second step, a step of forming a second gate region of second conductivity types on the channel layer, a step of forming a source electrode electrically connected to the layer of first conductivity type, and a step of forming a drain electrode electrically connected to the substrate of first conductivity type. A source-drain current is controlled by controlling a potential of at least one of the first street region and the second street region. By the same method, the SiC semiconductor device according to the seventh aspect can be manufactured.
[39] According to a nineteenth aspect of the present description, when the JFET is formed in the transistor cell region, the manufacturing method further comprises a step of forming a buried layer of first conductivity type in the first trench. The step of forming the buried layer of second conductivity type is performed after the step of forming the buried layer of first conductivity type. The step of forming the first ditch and the step of forming the second ditch are performed at the same time. The step of forming the buried layer of first conductivity type and the step of forming the channel layer are performed at the same time. The step of forming the buried layer of other conductivity types and the step of forming the second street region are performed at the same time. In such an approach, since a manufacturing process is commonly used, the electrically field relieving structure can be formed without an increase in the manufacturing process.
[40] According to a twentieth aspect of the present description, the manufacturing method further comprises a step of forming a MOSFET in the transistor cell region. The MOSFET has a base region provided by the layer of second conductivity types and a source region provided by the layer of first conductivity types. The step of forming the MOSFET comprises, after the step of forming a second trench which reaches the operating layer by penetrating the first conductivity layer and the second conductivity layer, a step of forming a deep layer of second conductivity layers in the second trench, a step of forming a gate insulating layer on a surface of the base region between the source region and the operating layer, a step of forming a gate electrode on a surface of the gate insulating layer, forming a source electrode electrically connected to the first conductivity type layer, and a step of forming a drain electrode electrically connected to the substrate of first conductivity type. A source-to-drain current is controlled by controlling a potential of the gate electrode. By this method, the SiC semiconductor device according to the ninth aspect can be manufactured.
[41] According to a twenty-first aspect of the present description, when the MOSFET is formed in the transistor cell region, the step of forming the first ditch and the step of forming the second ditch are performed simultaneously, and the step of forming the buried layer of others conductivity type and the step of forming the deep layer are performed at the same time. In such an approach, since a manufacturing process is commonly used, the electrically field relieving structure can be formed without an increase in the manufacturing process.
[42] According to a twenty-second aspect of the present description, when the MOSFET is formed in the transistor cell region, the manufacturing method further comprises a step of forming another trench in the transistor cell region such that the second trench is deeper than the second trench and when the operating layer by penetrating the layer of first conductivity type and the layer of second conductivity type. The gate insulating layer and the gate electrode are formed in what another ditch said the MOSFET has a ditch gate structure. By this method, the SiC semiconductor device according to the eleventh aspect can be manufactured.
[43] BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the present description will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. In the drawings: FIG. 1A illustrates top surface layout view of a SiC semiconductor device having a JFET according to a first embodiment of the present description, and FIG. 1B is a diagram illustrating a cross-sectional view taken along line IB-IB in FIG. 1A; FIG. 2 illustrates a graph showing a result of a supply of a ratio between a contaminant concentration of a P + type layer 15 and a drain breakdown voltage; FIG. 3A, 3B and 30 illustrate cross-sectional views showing manufacturing methods of the SiC semiconductor device shown in FIG. 1A and 1B; FIG. 4A, 4B and 40 illustrate cross-sectional views showing manufacturing methods of the SiC semiconductor device of FIG. 3A, 3B and 3C; FIG. 5 illustrates a cross-sectional view of a SiC semiconductor device having a JFET according to a second embodiment of the present description; FIG. 6 illustrates a cross-sectional view showing a manufacturing method of the SiC semiconductor device shown in FIG. 5; FIG. 7 illustrates a cross-sectional view of a SiC semiconductor device having a JFET according to a third embodiment of the present description; FIG. 8 illustrates a cross-sectional view showing a manufacturing method of the SiC semiconductor device of FIG. 7; FIG. 9 illustrates a cross-sectional view of a SiC semiconductor device having a JFET according to a fourth embodiment of the present description; FIG. 10 illustrates a cross-sectional view of a SiC semiconductor device having a MOSFET according to a fifth embodiment of the present description; FIG. 11A, 11B and 110 illustrate cross-sectional views showing manufacturing methods of the SiC semiconductor device shown in FIG. 10; FIGS. 12A, 12B and 120 illustrate cross-sectional views showing manufacturing methods of the SiC semiconductor device following FIG. 11A, 11B and 110; FIG. 13 illustrates a cross-sectional view of a SiC semiconductor device having a MOSFET according to a sixth embodiment of the present description; FIG. 14 illustrates a cross-sectional view showing a manufacturing method of the SiC semiconductor device shown in FIG. 13; FIG. 15 illustrates a cross-sectional view of a SiC semiconductor device having a MOSFET according to a seventh embodiment of the present description; FIG. 16 illustrates a cross-sectional view showing a manufacturing method of the SiC semiconductor device shown in FIG. 15; FIG. 17 illustrates a cross-sectional view of a SiC semiconductor device having a MOSFET according to an eighth embodiment of the present description; and FIG. 18A and 18B illustrate cross-sectional views showing methods for forming a P-type RESURF layer as an external voltage breakdown resistant structure.
[44] Embodiments of the present description are described with reference to the drawings in which male reference numerals indicate the same or equivalent parts.
[45] (First Embodiment) A SiC semiconductor device having a JFET is explained as an example of a SiC semiconductor device according to a first embodiment of the present description. FIG. 1A and 1B are diagrams illustrating a SiC semiconductor device having a JFET according to the present embodiment. FIG. 1A illustrates a top surface layout view, and FIG. 1B is an 11 cross-sectional view taken along line IB-IB in FIG. 1A. A structure of the SiC semiconductor device having the JFET according to the present embodiment is described below with reference to these diagrams.
[46] As shown in FIG. 1A and 1B, the structure comprises a transistor cell region (JFET-forming region) R1 where JFET cells are formed and an outer voltage break-through-resistant structure region R2 arranged around an outer periphery of the transistor cell region R1. In the transistor cell region R1, buried epitaxial regions R3, which are gate structures formed by filling the ditches with epitaxial layers, are arranged in a stripe sample. The external voltage breakthrough resistant structural region R2 surrounds the transistor cell region R1.
[47] The SiC semiconductor device is formed by using a semiconductor substrate 5 having a multilayer structure comprising an N + type substrate (a substrate of first conductivity type) 1, an N - type operating layer 2, a P + type layer (layers of other conductivity type) 3, and an Nr-type layer (a layer of first conductivity type) 4. For example, the N + -type substrate 1 has a N-type impurity concentration of 1x19 cm-3 or more. For example, a concentration of N-type impurity in the N-type operating layer 2 is lower than that of the N + -type substrate 1 and extends from 1x to 5x10 16 cm-3. For example, the P + type layer 3 has a concentration of P type impurity of from 1x18 to 5x1019 cm-3. For example, a concentration of N-type impurity in the Nr-type layer 4 is higher than that of the N-type operating layer 2 and ranges from 1x18 to 5x2 ° cm-3.
[48] In the SiC semiconductor device, the transistor cell region R1 is where many JFET cells are formed arranged on the center side of the semiconductor substrate 5, and the outer voltage breakthrough-resistant structural region R2 is arranged to surround the transistor cell region R1.
[49] A ditch 6 is formed on a major surface side of the semiconductor substrate 5 in the transistor cell region R1. The ditch 6 reaches the N - type operating layer 2 by penetrating the N + type layer 4 and the P + type layer 3. Sa as shown in FIG. 1A, the ditch has a longitudinal direction, and the multiple ditches 6 are arranged at predetermined intervals. An N-type channel layer (a fourth semiconductor layer) 7 is formed by epitaxial growth on an inner surface of ordinary ditch 6 and a P + -type layer (a fifth semiconductor layer) 8 is formed by epitaxial growth on the N-type channel layer 7. For example. the N-type channel layer 7 has a thickness of 1 μm or less and a concentration of N-type impurity of from 5x to 1x17 cm-3. For example, the P + type layer 8 has a concentration of P type impurities of from 1x18 to 5x cm-3. The ditch 6 is filled with the N-type channel layer 7 and the Pf-type layer 8 so that the buried epitaxial regions R3 can be formed. In the transistor cell region R1 where JFET cells are formed, a first gate region is provided by the P + type layer 3, a second gate region is provided by the P + type layer 8, and an N + type source region is provided by the N + type layer 4.
[51] Although not shown in the drawings, the P + type layer 3, which provides the first gate region, is electrically connected to a first gate electrode, and a gate voltage of the first gate region is controlled by the first gate electrode. Furthermore, the P + type layer 8, which provides the second gate region, is electrically connected to a second gate electrode 9, and a gate voltage of the second gate region is controlled by the second gate electrode 9.
[52] For example, the first gate electrode is formed on a surface of the P + type layer 3, which provides the first gate region, in such a way that it is visible in cross section other than that shown in FIG. 1B. The first gate electrode is in contact with the P + type layer 3 through a contact hall. The second gate electrode 9 is formed on a surface of the P + type layer 8, which provides the second gate region. For example, each of the first gate electrode and the second gate electrode are formed by forming an alloy layer of Ti and Al on Ni, which is a material which can form an ohmic contact with a Pf type semiconductor. Furthermore, a source electrode 10, which is made of Ni or the like, is formed on a surface of the N + type layer 4, which provides the N + type source region. The source electrode 10 is electrically isolated from the first gate electrode and the second gate electrode 9 by a dielectric intermediate layer 11.
[54] A drain electrode 12 is formed on a back surface of the semiconductor substrate 5 and electrically connected to the N + type substrate 1. In this way, JFET cells are formed in the transistor cell region R1
[55] A trench (first trench) 13 is formed on the main surface side of the semiconductor substrate 5 in the outer voltage breakdown-resistant structural region R2. The ditch 13 reaches the N-type operating layer 2 by penetrating the N + -type layer 4 and the P + -type layer 3. The ditch 13 surrounds the periphery of the transistor cell region R1 to form a closed loop around the transistor cell region R1. An N-- type layer (a buried layer of first conductivity type) 14, which is formed simultaneously with the N-- type channel layer 7, and a P + type layer 15 (a buried layer of second conductivity types) 15, which is formed simultaneously with The P + type layer 8, are provided in the ditch 13. Furthermore, a recess 16 and a recess 17 are formed on the main surface side of the semiconductor substrate 5. The recess 16 is deeper than the thickness of the N + type layer 4. The recess 17 is arranged outside the recess 16 and when The N-type 13 operating layer 2 by penetrating the Nr-type layer 4 and the P + -type layer 3. The recess 16 corresponds to a second recess, and the recess 17 corresponds to a first recess. In this way the mesa structure is formed. The viii saga, in the mesa structure, the recess 17 surrounds the transistor cell region R1 and the recess 16 is arranged inside the recess 17 and surrounds the transistor cell region R1.
[56] A P-type region 18 is formed on an outer edge of a bottom surface of the recess 16, i.e. formed on the adjacent surface of the bottom surface of the recess 16 to the recess 17 to surround the transistor cell region R1. For example, the P-type region 18 has a concentration of P-type contaminant of from 1x18 to 5x cm-3 (e.g. 5x18 cm-3). A P-type region 19 is formed on the adjacent surface of a bottom surface of the recess 17 to a boundary between the bottom surface and a side surface of the recess 17, i.e. formed on the adjacent surface of the bottom surface of the recess 17 to the recess 16 to surround the transistor cell region R1. For example, the P-type region 19 has a concentration of P-type contaminant of from 1x18 to 5x2 ° cm-3 (e.g. 5x18 cm-3). The ditch 13 is arranged at the boundary (at a step height part) between the bottom surface and the side surface of the recess 17, and the side surface of the recess 17 is provided by the Pf-type layer 15 in the trench 13. Thus, the P-type region 18 is on the bottom surface of the recess 16. The P + type layer 15 in the ditch 13 and the P type region 19 on the bottom surface of the recess 17 joined together to form a P type RESURF layer 20. This P type RESURF layer 20 provides an electrically folded relief structure.
[57] Furthermore, in the outer voltage breakthrough resistant structural region R2, an N + type layer 21 is formed in a surface portion of the N - type operating layer 2 on the bottom surface of the recess 17. The N + type layer 21 is arranged outside the P-type RESURF layer. 20 and connected to an electrode 22. The N + type layer 21 and the electrode 22 provide a channel stop (EQR) for cutting electric field.
[58] The SiC semiconductor having a JFET according to the present embodiment has a structure as described above.
[59] In the SiC semiconductor having the above structure, the JFET in the transistor is normally ay. An operation of the JFET is controlled by voltages applied to the first gate electrode and the second gate electrode 9 in the following manner.
[60] When the first gate electrode and the second gate electrode 9 are electrically connected to each other so that the potentials of these electrodes can be controlled to be the same, or when the first gate electrode and the second gate electrode 9 are electrically disconnected from each other so that the potentials of these electrodes can be controlled separately, a two-gate drive is performed. That is, the amount of extension of a depletion layer extending from the P + type layers 3, 8, which provide the first and second gate regions, to the 14 N - type channel layer 7 is controlled based on the potentials of the first gate electrode and the second gate electrode 9. For example, when no voltage is applied to the first gate electrode and the second gate electrode 9, the N-type channel layer 7 is throttled by the depletion layer extending from the P + type layers 3, 8. As a result, a source-to-drain is closed -strom ay. Then, when a bias is arranged between the P + type layers 3, 8 and the N - type channel layer 7, the amount of extension of the depletion layer extending towards the N - type channel layer 7 is reduced. As a result, a channel region is formed so that a source-to -drain-stream can flood.
[61] Furthermore, in the SiC semiconductor having the above structure, the P-type region 18 on the bottom surface of the recess 16 forms the P + type layer 15 in the trench 13 and the P-type region 19 on the recess 17 The P-type RESURF layer 20 in the external voltage breakthrough resistant structural region R2. Since the P-type RESURF layer 20 surrounds the periphery of the transistor cell region R1, the concentration of electric field at a horn is relieved, which defines the boundary between the side surface and the bottom surface. Therefore, a breakthrough position is moved to the N-type operating layer 2 on the bottom surface of the recess 17. Thus, the electric field is relieved so that a drainage breakdown voltage can be improved.
[62] FIG. 2 is a graph showing a result of a feed of a relationship between the contaminant concentration of the P + type layer 15 and the tensile breakdown voltage when the P + type layer 15 is arranged at the boundary (the step-up portion) between the bottom surface and the side surface of the recess 17. A drainage breakdown voltage observed When the Pf-type layer 15 is not arranged at the boundary between the bottom surface and the side surface of the recess 17, it is also shown in FIG. 2 for reference.
[63] Sa as shown in FIG. 2, when the P + type layer 15 is provided at the boundary between the bottom surface and the side surface of the recess 17, the breakthrough voltage is greatly improved compared with when the P + type layer 15 is not provided. In particular, when the P-type contaminant is greater than 3.0x17 cm-3 or more, the ground breaking voltage may be higher than 1100V. Therefore, the P-type pollutant is set to greater than 3.0x17 cm-3 or more so that the drain breakdown voltage can be higher than 1100V. According to the present embodiment, the P + -type layer has the P-type impurity of from 1x18 to 5x2 ° cm-3 (e.g. 5x18 cm-3) to ensure a high tensile breakdown voltage.
[64] Most recently, a manufacturing method of the SiC semiconductor device shown in FIG. 1A and 1B with reference to FIG. 3A, 3B and 30 and FIG. 4A, 4B and 40. In FIG. 3A, 3B and 30 and FIG. 4A, 4B and 40 are a portion outside the P-type RESURF layer 20 shown in FIG. 1B omitted.
[65] (Method shown in FIG. 3A) First, the N + type substrate 1 having the impurity concentration described above is prepared. Thereafter, the No. type operating layer 2, the P + type layer 3, and the N + type layer 4 are formed in turn by epitaxial growth on the surface of the N + type substrate 1. As a result, the semiconductor substrate 5 is made.
[66] (Method shown in FIG. 3B) By photolithography, the ditch 6, which reaches the Nr-type operating layer 2, is formed by penetrating the N + -type layer 4 and the P + -type layer 3, in the transistor cell region R1 at the same time as the ditch 13, which reaches N type operating layer 2 by penetrating the N + type layer 4 and the P + type layer 3, are formed in the external voltage breakthrough resistant structural region R2. According to the present embodiment, each of the ditches 6 and 13 has the same width and the same depth.
[67] (Method shown in FIG. 3C) By epitaxial growth, Nr-type SiC and P + -type SiC are epitaxially grown on the entire surface of the semiconductor substrate 5 to form the Nr-type layer 30 and the P + -type layer 31 so that the ditches 6 and 7 can be filled with the No. type layer 30 and the P + type layer 31.
[68] (Method shown in FIG. 4A) The surface of the semiconductor substrate 5 is flattened by back etching or CMP (chemical mechanical polishing) so that the Nr-type layer 30 and the P + -type layer 31 can remain only in ditches 6 and 13. Thus, The Nr-type channel layer 7 and the P + -type layer 8 formed in the ditch 6, and the Nr-type layer 14 and the Pf-type layer 15 are formed in the ditch 13.
[69] (Method shown in FIG. 4B) By anisotropic etching such as RIE (reactive ion etching), an outer edge of the transistor cell region R1 is etched to a depth deeper than the N + type layer 4, so that the recess 16 is formed. Specifically, the recess 16 is formed by performing anisotropic etching that after a mask having an aperture corresponding to a forming region of the recess 16 (the outer stress breakthrough structural region R2) where the recess 16 is to be formed has been placed. Then, by anisotropic etching such as RIE using another mask, the outer edge of the bottom surface of the recess 16 is selectively etched to a depth deeper than the Pf-type layer 3, so that the recess 17 is formed. Specifically, the recess 17 is formed by performing anisotropic etching after the second mask having an opening corresponding to a forming region of the recess 17 (a region from a first position where the P-type RESURF layer 15 is to be formed to a second position outside the first the position) where the recess 17 is to be formed has been placed. In this way 16 the mesa structure is formed. At this time, the side surface of the recess 17 is provided with the P + type layer 15.
[70] (Method shown in FIG. 4C) After a mask 32 for ion implantation is placed, openings corresponding to formation regions of P-type regions 18 and 19 are formed. Thereafter, the P-type regions are formed by performing ion-implantation of P-type contaminants in the direction is normal to the substrate surface. At this time, since the side surface of the recess is provided, the P + type layer 15 in the method shown in FIG. 4B, the P-type region 18 on the bottom surface of the recess 16, the P + type layer 15 in the trench 13 and the P-type region 19 on the bottom surface of the recess 17 joined together to form the P-type RESURF layer 20.
[71] When the openings are formed in the mask 32, some remnant of the mask 32 may remain on the side surface of the recess 17. The rest may block the ion implantation so that a spirit of the P-type region 19 may be somewhat separated from the horn of the recess 17. Since P + The type-type layer 15 in the ditch 13 is also arranged on the bottom surface of the recess 17, however, the Pf-type layer 15 and the P-type region 19 are continuously joined to each other.
[72] Although subsequent methods are not shown in the drawings, after the mask 32 is removed, ion implantation of N-type contaminants is performed using a metal mask or the like. Then the implanted ions are activated, so that the N + -type layer 21 Ors. Then, after the dielectric intermediate layer 11 is formed on the entire surface of the semiconductor substrate 5, contact predetermined regions are formed of the dielectric intermediate layer 11 and the No. type layer 4. Then, a lead layer is formed on the dielectric intermediate layer 11, and the first gate electrode, the second gate electrode 9. , the source electrode 10 and the electrode 22 are formed by sampling the lead layer. Thereafter, the drain electrode 12 p5 is formed on the back surface of the semiconductor substrate 5. P5 this way, the SiC semiconductor device shown in FIG. 1A and 1B.
[73] As described above, in the SiC semiconductor device according to the present embodiment, the P-region 18 p5 forms the bottom surface of the recess 16, the P + type layer 15 in the trench 13 and the P-type region 19 on the bottom surface of the recess 17 P-type RESURF layer 20 to provide the electrically field relieving structure. Since the P-type RESURF layer 20 surrounds the periphery of the transistor cell region R1, the concentration of electrical fait at the horn is relieved, which defines the boundary between the side surface of the bottom surface. Therefore, the breakthrough position is moved to the N-- type operating layer 2 p5 the bottom surface of the recess 17. Thus, the electric field is relieved so that the tensile breakdown voltage can be improved. In particular, according to the present embodiment, the P-type region 18, the P + type layer 15 and the P-type region 19 are continuously joined together to form the P-type RESURF layer 20. Thus, an ideal drain breakdown voltage at the time of AV sakerstallas.
[74] The P-type RESURF layer 20 can be formed without implanting ions in the side surface of the recess 17 during ion implantation, as long as the P-type regions 18 and 19 are formed on the bottom surfaces of the recess 16 and the recess 17. Therefore, the P-type The RESURF layer 20 is formed without performing inclined ion implantation. Thus, the external voltage breakthrough resistant structure is formed, which surrounds the periphery of the transistor cell region R1 where the JFET is formed, without performing the inclined ion implantation, so that the SiC semiconductor device has a structure for achieving a high voltage breakdown voltage. The ditch 13, the N-type layer 14 and the P + -type layer 15 to provide the structure are formed at the same time as the ditch 6, the N-type layer 7 and the P + -type layer 8 to provide the JFET. Since the manufacturing process is commonly used, the structure can be formed without an increase in the manufacturing process.
[75] (Second Embodiment) A second embodiment of the present disclosure is described. Since the present embodiment is the same as the first embodiment except for a structure of the external voltage breakthrough resistant structural region R2, only the difference is described.
[76] FIG. 5 is a diagram illustrating a cross-sectional view of a SiC semiconductor device having a JFET as described herein. S5 shown in FIG. 5, multiple ditches 13 are formed, and each ditch is filled with the N-type layer 14 and the P + -type layer 15. The innermost ditch 13 closest to the transistor cell region R1 is arranged at the boundary (at a step height portion) between the bottom surface and the side surface of the recess 17. , and the side surface of the recess 17 is provided by the P + type layer 15 in the innermost ditch 13. Although upper parts of the P + type layer 15 in the other ditches 13 arranged outside the innermost ditch 13 are removed by the recess 17, the remaining parts are P + type layers 15 arranged at regular intervals to provide a protective ring structure.
[77] As described above, according to the present embodiment, the protective ring structure is formed in the outer voltage breakdown-resistant structural region R2 instead of the P-type RESURF layer 20 according to the first embodiment. Even when the protective ring structure is formed, the P + type layer 15 can be arranged on the side surface of the recess 17 by using ditch 13, the N - type layer 14, and the P + type layer 15. Thus, the same advantages as the first embodiment can be obtained.
[78] A manufacturing method of the SiC semiconductor device according to the present embodiment is almost the same as that described in the first embodiment. As shown in FIG. 6 is a difference that multiple ditches 13 are formed at regular intervals in the process as described in the first embodiment with reference to FIG. 3B. When multiple ditches 13 are formed at regular intervals in advance, each ditch 13 is filled with the N - type layer 14 and the P + type layer 15.
[80] FIG. 7 is a diagram illustrating a cross-sectional view of a SiC semiconductor device having a JFET as described herein. As shown in FIG. 7, according to the present embodiment, although the protective ring structure is formed by using the ditch 13, the N-type layer 14 and the Pf-type layer 15, the ditches 13 are arranged in descending order of their width in an outward direction. Furthermore, when the ditch 13 is narrower, the N-type layer 14 is thicker so that the P + -type layer 15 on the N-type layer 14 may be thinner.
[81] As the depth of the P + type layers 15 continuously decreases, the electric field is further relieved at the time of OFF. Therefore, even though the size of the external voltage breakthrough resistant structural region R2 is smaller than that of the second embodiment in which the Pf type layers 15 have the same depth, the same or higher tensile breakdown voltage can be set.
[82] A manufacturing method of the SiC semiconductor device according to the present embodiment is almost the same as that described in the second embodiment. As shown in FIG. 8 is a difference that the ditches 13 are arranged in descending order of their width in the outward direction in the method described in the first embodiment with reference to FIG. 3B. When the ditches 13 are arranged in descending order of their width in an outward direction in advance, the thickness of the N-type layer 14 formed at the bottom of the ditch 13 changes according to the width of the ditch 13. Therefore, when the ditches 13 are narrower, N-- type layer 14 thicker so that the P + type layer 19 on the N - type layer 14 may be thinner. In this way, the SiC semiconductor device is manufactured according to the present embodiment.
[83] [0083] (Fourth Embodiment) A fourth embodiment of the present description is described. Since the present embodiment is the same as the second and third embodiments except for one form of the protective ring structure, only the difference is described.
[84] FIG. 9 is a diagram illustrating a cross-sectional view of a SiC semiconductor device having a JFET as described herein. In the second and third embodiments, the innermost ditch 13 of the multiple ditches 13 formed in the outer stress breakthrough structural region R2 is arranged at the boundary (at a step height portion) between the bottom surface and the side surface of the recess 17. However, it is not always necessary that the innermost the layer 13 is arranged at the border. For example, as shown in FIG. 9, the Nth ditch 13 from the innermost ditch 13, where N is a positive integer, may be arranged at the boundary (at a step height portion) between the bottom surface and the side surface of the recess 17. In other words, at least eft ditch 13 may be arranged inside the ditch 13 which is arranged at the boundary between the bottom surface and the side surface of the recess 17.
[85] In the protective ring structure, the N-type layer 14 and the N-type operating layer 2 operate, which are arranged between P-type regions with one inside the second (P + -type layers 15 in the ditches 13 according to the second and third embodiments, and the present embodiments) as the electrical fait relieving structure. When the innermost ditch 13 of the multiple ditches 13 formed in the outer stress breakthrough structural region R2 is provided at the boundary (at a step height portion) between the bottom surface and the side surface of the recess 17 as in the second and third embodiments, only the P + type layers 15 in recessed 17 protective ring structure. Therefore, a distance between adjacent protective ring structures is the same as the sum of the thickness of the N-type layers 14 in adjacent ditches 13 and the width of the N-type operating layer 2 between adjacent ditches 13.
[86] In contrast, according to the present embodiment, the protective ring structure formed by the ditch 13, the N-type layer 14 and the Pf-type layer 15 are also provided in the recess 16 so that the P + -type layer 3 can be arranged between the ditches 13. Thus, not only the P + type layers 15 but also the P + type layer 3 as the protective ring structure, and depending on the distance between adjacent protective ring structures is the same as the thickness of the N - type layers 14 only. Accordingly, electrical fait in the guard ring structure is reduced so that a stable drain breakdown voltage can be easily maintained.
[87] In FIG. 9, each ditch 13 has the same width as in the second embodiment. The same grid for the ditches 13 is arranged in descending order of its width in the outward direction as in the third embodiment.
[88] [0088] (Fifth Embodiment) A fifth embodiment of the present description is described. Since the present embodiment is the same as the first embodiment except for a transistor formed in the transistor cell region R1, only the difference is described.
[89] FIG. 10 is a diagram illustrating a cross-sectional view of a SiC semiconductor device according to the present embodiment. As shown in FIG. 10, according to the present embodiment, the SiC semiconductor device has a MOSFET with a ditch gate structure. Specifically, according to the present embodiment, the SiC semiconductor device is formed by using a semiconductor substrate 5 having a multilayer structure comprising N + type substrate (a substrate of first conductivity type) 1, an N1 type operating layer (a layer of first conductivity type) 2, a P + type layer (layers of other conductivity types) 3, and an N + type layer 4. The P + type layer 3 acts as a P-type base region to form a channel region. A gate insulating layer 40 and a gate electrode 41 on the surface of the gate insulating layer 40 are formed in the ditch 6 'instead of the N1-type channel layer 7 and the P + type layer 8. The ditch 6' is filled with the gate-insulated layer 40 and the gate electrode 41.
[90] Furthermore, a ditch (second ditch) 42, which reaches the I 1 type operating layer 2 by penetrating the N + type layer 4 and the P + type layer 3, is formed in the transistor cell region R1. The ditch 42 is deeper than the ditch 6 'and separated from a side surface of the ditch 6' by a predetermined distance. The ditch 42 is filled with a Pf-type deep layer 43. Since the ditch 42 is deeper than the ditch 6 ', an electric field provided to the gate insulating layer 40 at the time of AV is reduced so that a breakthrough of the gate insulating layer 40 can be prevented. A P-type or N1-type layer concentration layer 44 is formed on a bottom surface of the ditch 42 so that a corner of a P + type deep layer 43 may be rounded to reduce the concentration of electric field. Alternatively, the trench 42 can be filled with the P + type deep layer 43 only.
[91] The dielectric intermediate layer 11 thanks the gate electrode 41. The source electrode is formed on the dielectric intermediate layer 11. The source electrode 10 is electrically connected to the N + type layer 4, which provides a source region, through the contact hole of the dielectric intermediate layer 11. The source electrode 10 is also electrically connected to the P + type layer 3, which provides the 21 P-type base region, through the contact hole in the dielectric intermediate layer 11 and the P + type deep layer 43. In this way, the MOSFET with the ditch gate structure is formed.
[92] A trench (first trench) 45 is formed on the main surface of the semiconductor substrate 5 in the outer voltage breakthrough resistant structural region R2. The ditch 45 reaches the N-type operating layer 2 by penetrating the kr-type layer 4 and the P + -type layer 3. The ditch 45 surrounds the periphery of the transistor cell region R1 to form a closed loop around the transistor cell region R1. A P + type layer (a buried layer of second conductivity type) 46, which is formed at the same time as the P + type deep layer 43, and a layer concentration layer (a buried layer of first or second conductivity type) 47, which is formed at the same time as the long concentration layer 44 , are provided in the ditch 45.
[93] The trench 45 is arranged at the boundary (at a step-high part) between the bottom surface and the side surface of the recess 17, and the side surface of the recess 17 is provided by the P + -type layer 46 in the trench 45.
[94] As described above, even when the SiC semiconductor device has the MOSFET having the ditch gate structure, the side surface of the recess 17 may be provided with the P + type layer 46 in the ditch 45. Thus, the same advantages as the first embodiment can be obtained.
[95] Most recently, a manufacturing method of the SiC semiconductor shown in FIG. 10 with male reference to FIG. 11A, 11B and 11C, and FIG. 12A, 12B and 12C. In FIG. 11A, 11B and 11C, and FIG. 12A, 12B and 120 are a portion outside the P-type RESURF layer 20 shown in FIG. excluded.
[96] (Method shown in FIG. 11A) Hirst prepares the N + type substrate 1 having the impurity concentration described above.
[98] (Method shown in FIG. 11C) By epitaxial growth, P - type or N - type SiC and P + type SiC are epitaxially grown on the entire surface of the semiconductor substrate 5 to form the layer concentration layers 44 and 47, the Pf type deep layer 43. and the P + type layer 46 said that the ditches 42 and 45 can be filled with these layers.
[99] (Method shown in FIG. 12A) The surface of the semiconductor substrate 5 is flattened by back-etching or CMP (chemical mechanical polishing) so that the layer concentration layers 44 and 47, the P + type deep layer 43 and the P + type layer 46 can remain only in the trenches 42. and 45.
[100] (Method shown in FIG. 12B) The recesses 16 and 17 are formed by performing the same procedure as described in the first embodiment with reference to FIG. 4B. Thus the mesa structure is formed. At this time, the side surfaces of the recess 17 are provided with the P + type layer 46 in the trench 45.
[101] (Method shown in FIG. 120) The ditch 6 'is formed by performing ditch etching after a ditch etching mask (not shown) has been placed on the entire surface of the semiconductor substrate 5. Thereafter, the gate insulating layer 40 is formed by thermal oxidation. Thereafter, the gate electrode 41 is formed by depositing doped polycrystalline silicon or the like. Then flattening is performed by back-etching or the like so that the gate electrode can remain in the ditch 6. Although subsequent methods are not shown in the directions, as in the method shown in FIG. 40 of the first embodiment, after an ion implantation mask having apertures corresponding to P-type region regions 18 and 19 is placed, P-type ion implantation is performed in the direction normal to the substrate surface. As a result, the P-type regions 18 and 19 are formed at this time, since the side surface of the recess 17 is provided by the Pf-type layer 46 in the trench 45 in the process shown in FIG. 12B, the P-type region 18 on the bottom surface of the recess 16, the P + type layer 46 in the ditch 13, and the P-type region 19 on the bottom surface of the recess 17 are joined together to form the P-type RESURF layer 20. Thereafter, after the mask has been removed, ion implantation of N-type contaminants is performed using a metal mask or the like. Then the implanted ions are activated so that the N + type layer 21 Ors. Then, after the dielectric intermediate layer 11 is formed, contact halls are formed in predetermined regions of the dielectric intermediate layer 11 and the N + type layer 4. 23 . Thereafter, the drain electrode 12 is formed on the back surface of the semiconductor substrate 5. In this way, the SiC semiconductor device shown in FIG. 10.
[103] As described above, in the SiC semiconductor device according to the present embodiment, the P-type region p5 forms the bottom surface of the recess 16, the P + type layer 46 in the trench 45, and the P-type region 19 p5 the bottom surface of the recess 17 P-type RESURF layer 20. Thus, as in the first embodiment, the rotational breakdown voltage can be improved.
[104] The P-type RESURF layer 20 can be formed without implanting ions in the side surface of the recess 17 during ion implantation. Therefore, the P-type RESURF layer 20 can be formed without performing the inclined ion implantation. Thus, the external voltage breakthrough resistant structure is formed around the periphery of the transistor cell region R1, where the MOSFET is formed, without performing the inclined ion implantation, so that the SiC semiconductor device has a structure to provide a high voltage breakdown voltage. The trench 45 and the P + type layer 46 to provide the structure are formed at the same time as the trench 42 and the P + type deep layer 43 to provide the MOSFET. Therefore, the structure can be formed without an increase in the manufacturing process.
[105] [0105] (Sixth Embodiment) A sixth embodiment of the present disclosure is described. Since the present embodiment is the same as the fifth embodiment except for a structure of the external voltage breakthrough-resistant structural region R2, only the difference is described. FIG. 13 is a diagram illustrating a cross-sectional view of a SiC semiconductor device having a MOSFET according to the present embodiment. As shown in FIG. 13, multiple ditches 45 are formed, and each ditch 45 is filled with the layer concentration layer 47 and the P + type layer 46. The innermost ditch 45 closest to the transistor cell region R1 is arranged at the boundary (at a step height portion) between the bottom surface and the side surface of the recess 17, and the side surface of the recess 17 is provided by the Pf-type layer 46 in the innermost ditch 45. Although upper parts of the P + -type layer 46 in the other ditches 45 arranged outside the innermost ditch 45 are removed by the recess 17, the remaining parts of the P + - type layers 46 arranged at regular intervals to provide the protective ring structure.
[107] As described above, according to the present embodiment, the protective ring structure formed in the outer voltage breakthrough resistant structural region R2 is instead of the P-type RESURF layer 20 according to the fifth embodiment. Even when the protective ring structure is formed, the P-24 type layer 46 can be arranged on the side surface of the recess 17 by using the ditch 45 and the P + -type layer 46. Thus, the same advantages as the fifth embodiment can be obtained. A manufacturing method in which the SiC semiconductor device according to the present embodiment is almost the same as that described in the fifth embodiment. As shown in FIG. 14 is a difference that multiple ditches 45 are formed at regular intervals in the process which is described in the fifth embodiment with reference to FIG. 11B. When the multiple ditches 45 are formed at regular intervals in the precast, the selected ditch 45 is filled with the layer concentration layer 47 and the Pf-type layer 46 by forming the layer concentration layer 44 and the P + type deep layer 43.
[109] [0109] (Seventh Embodiment) A seventh embodiment of the present disclosure is described. Since the present embodiment is the same as the sixth embodiment except for one form of the protective ring structure, only the difference is described.
[110] FIG. 15 is a diagram illustrating a cross-sectional view of a SiC semiconductor device having a MOSFET according to the present embodiment. As shown in FIG. 15, according to the present embodiment, although the protective ring structure is formed by using the ditch 45, the layer concentration layer 47, and the P + type layer 46, the ditches 45 are arranged in descending order of their width in the outward direction. Furthermore, when the ditch 45 is narrower, the layer concentration layer 47 in the ditch 45 is thicker so that the P + type layer 46 on the layer concentration layer 47 may be thinner.
[111] In this structure, the electric field is further relieved at the time of AV. Therefore, even when the size of the external voltage breakthrough resistant structural region R2 is smaller than that of the sixth embodiment in which the P + type layers 46 have the same depth, the same or higher tensile breakthrough voltage can be set.
[112] A manufacturing method of the SiC semiconductor device according to the present embodiment is almost the same as that described in the sixth embodiment. As shown in FIG. 16 is a difference that the grooves 45 are arranged in descending order of their width in the outward direction of the method which is described in the fifth embodiment with reference to FIG. 11B. When the ditches 45 are arranged in descending order of their width in the outward direction, the thickness of the igneous concentration layer 47 formed on the bottom of the ditch 45 in accordance with the width of the ditch 45. Therefore, when the ditch 45 is narrower, the layer concentration layer 47 is thicker so that P + - type layer 46 on the layer concentration layer may be thinner. P5 this way, the SiC semiconductor device is manufactured according to the present embodiment.
[113] (Eighteenth embodiment) An eighth embodiment of the present description is described. Since the present embodiment is the same as the sixth and seventh embodiments except for one form of the protective ring structure, only the difference is described.
[114] FIG. 17 is a diagram illustrating a cross-sectional view of a SiC semiconductor device having a MOSFET according to the present embodiment. In the sixth and seventh embodiments, the height of the bottom surface of the recess 17 formed in the outer stress breakthrough-resistant structural region R2 is kept constant. Alternatively, as shown in FIG. 17, the height of the bottom surface of the recess 17 may gradually decrease in the outward direction of the transistor cell region R1. P5 so set, the P + type layers 46 have the protective ring structure arranged in descending order of their height so that the outermost P + type layer 46 may have the minimum height.
[115] When the Pf-type layers 46 have the protective ring structure arranged in descending order of their height, the electric field is effectively relieved. According to P5, the breakthrough voltage is further improved.
[116] (Modifications) Although the present description has been described with reference to embodiments thereof, it is to be understood that the description is not limited to the embodiments. The present description is intended to encompass various modifications and equivalent devices within the spirit and scope of the present description.
[117] In the above embodiments, the electrically relieving structure is provided by forming the side surface of the recess 17 at the boundary between the recess 16 and the recess 17 using the P + type layer 15 or 46, and the outer voltage breakdown resistant structure is provided by forming the P type The RESURF layer 20 or the protective ring structure using it. The minimum requirement for such an external voltage breakthrough resistant structure is to include the electrically light-relieving structure which is provided by forming the side surface of the recess 17 at the boundary between the 26 recess 16 and the recess 17 using the P + type layer 15 or 46. The external voltage breakthrough resistant structure may which heist sat as long as the minimum requirement is met. For example, the external voltage breakthrough resistant structure may be the P-type RESURF layer 20 using the electrically relieving structure, the protective ring structure using the electrically relieving structure, or a combination thereof.
[118] In the above embodiments, an N-channel type JFET in which a channel region is created in the N-type channel layer 7 or an N-channel type MOSFET in which a channel region is created in the P + type layer 3 which provides the P-type base region described as eft examples. Alternatively, a P-channel type JFET or MOSFET in which after conductivity type of habit component is inverted can be applied to the present description. Although a JFET or a MOSFET is described as an example of a transistor formed in the transistor cell region R1, another type of transistor may be formed.
[119] In the first embodiment, the JFET is driven by a two-gate drive in which the source-todrain stream is controlled by controlling the potential of habit of the first and second gate regions. Alternatively, the JFET may be driven by an engates drive in which the source-to-drain stream is controlled by controlling the potential of one of the first and second gate regions.
[120] In the above embodiments, the N + type layer 4, which provides the source region, is formed by epitaxial growth. Alternatively, the N + type layer 4 may be formed by ion implantation of N type impurities in the first street region 3. In this case, when the Nr type layer 4 is formed at a position separated from the mesa structure, there is no need to form the recess 16.
[121] In the SiC semiconductor device having the JFET in the transistor cell region R1 according to the first to the fourth embodiment, since the ditch 13 corresponding to the first ditch and the ditch 6 corresponding to the second ditch can be formed simultaneously, the electrical fait relieving structure is formed so as the P-type RESURF layer 20 or the protective ring structure by using the ditch 13 filled with the N-type layers 14 and the P + -type layer 15. In the same way, in the SiC semiconductor device having the MOSFET in the transistor cell region R1 according to the fifth to the eighth embodiment, since the ditch 45 corresponding to the first ditch and the ditch 42 corresponding to the second ditch can be formed simultaneously, the electrical fait relieving structure such as the P-type RESURF layer 20 or the protective ring structure is formed by using the ditch 42 filled with P + - type layer 42. Alternatively, in the SiC semiconductor device having the JFET, the 27 electrically fait relieving structure may be said as the P-type RESURF layer 20 or protective ring structure. The curve is formed by using the ditch 42 filled P + type layer 42 as described in the fifth to eighth embodiments, or in the SiC semiconductor device having the MOSFET, the electrically fold relieving structure such as the P-type RESURF layer or the protective ring structure formed by using the ditch 13 filled with the Nr-type layers 14 and the P + -type layer 15. 28

权利要求:
Claims (22)
[1]
A silicon carbide semiconductor device comprising: a semiconductor substrate (5) comprising a substrate (1) of first conductivity type, an operating layer (2) of first conductivity type p5 the substrate (1) of first conductivity type, a layer (3) of second conductivity types p5 the operating layer (2) , and a layer (4) of first conductivity type p5 layer (3) of second conductivity types; a transistor formed in a transistor cell region (R1) of the semiconductor substrate (5); and an outer voltage breakthrough resistant structure formed in an outer voltage breakthrough resistant structural region (R2) surrounding an outer periphery of the transistor cell region (R1), the outer voltage breakthrough resistant structure formed in an outer voltage breakthrough resistant structural region (R2) comprising the periphery of the transistor cell region (R1), a first ditch (13, 45) arranged at a side surface of the first recess (17) on an inner periphery of the first recess (17), and an electrically folded relieving structure having a buried layer (15); , 46) of second conductivity type, the first recess (17) is deeper than the layer (4) of first conductivity type and the layer (3) of second conductivity type and when the operating layer (2), the first trench (13, 45) surrounds the outer periphery of the transistor cell region (R1), and the buried layer (15, 46) of other conductivity types is buried in the first ditch (13, 45) and provides side surface n of the first recess (17).
[2]
The silicon carbide semiconductor device according to claim 1, further comprising: a second recess (16) deeper than a thickness of the layer (4) of first conductivity type and surrounding the outer periphery of the transistor cell region (R1), the first recess (17) being arranged further away from the transistor cell region (R1) to the second recess (16) and deeper than the second recess (16), and the first trench (13, 45) is arranged at a boundary between the first recess (17) and the second recess (16). .
[3]
The silicon carbide semiconductor device according to claim 2, wherein the layer (18, 19) of second conductivity type is formed on an adjacent side of a bottom side of the second recess (16) to the first recess (17), formed on an adjacent side of a bottom side of the first recess (17) to the second recess (16), and joined to the buried layer (15, 46) of second conductivity types to form a RESURF layer (20) of second conductivity types which provides the electrically relieved structure.
[4]
The silicon carbide semiconductor device according to claim 2, further comprising a plurality of first ditches (13, 45) comprising the first ditch (13, 45), the plurality of first ditches (13, 45) being arranged outwardly from the boundary between the first recess ( 17) and the second recess (16), and the buried layer (15, 46) of second conductivity type is buried in each of the plurality of the first ditches (13, 45) to form a protective ring structure which provides the electrically relieving structure. .
[5]
The silicon carbide semiconductor device according to claim 2 or 4, further comprising a plurality of first ditches (13, 45) comprising the first ditch (13, 45), the plurality of first ditches (13, 45) being arranged food from the boundary between the first recess ( 17) and the second recess (16), and the buried layer (15, 46) of second conductivity type is buried in each of the plurality of first ditches (13, 45) to form a protective ring structure which provides the electrically relieving structure. .
[6]
The silicon carbide semiconductor device according to claim 4 or 5, wherein the plurality of first ditches (13, 45) are arranged in descending order of their width in an outward direction of the transistor cell region (R1).
[7]
A silicon carbide semiconductor device according to any one of claims 1-6, wherein a JFET is formed in the transistor cell region (R1) and comprises a first gate region, a source region, a second trench (6), a channel layer (7) of first conductivity type, a second gate region ( 8) of second conductivity types, a source electrode (10), and a drain electrode (12), the first gate region is provided by the layer (3) of second conductivity types, the source region is provided by the layer (4) of first conductivity types, the second ditch (6 ) when the operating layer (2) by penetrating the layer (4) of the first conductivity type and the layer (3) of second conductivity types, the channel layer (7) is formed by epitaxial growth on an inner cradle of the second ditch (6), the second street region (8 ) is formed on the channel layer (7), the source electrode (10) is electrically connected to the layer (4) of first conductivity type, the drain electrode (12) is electrically connected to the substrate (1) of first conductivity type, and a source-to-drain current is controlled by controlling a potential of at least one of the first gate region (3) and the second gate region (8).
[8]
The silicon carbide semiconductor device according to claim 7, wherein the first trench (13) and the second trench (6) have the same depth, and the buried layer (15) of second conductivity type is formed on a buried layer (14) of first conductivity type in the first diket (13).
[9]
A silicon carbide semiconductor device according to any one of claims 1 to 6, wherein a MOSFET is formed in the transistor cell region (R1) and comprises a base region, a source region, a gate insulating layer (40), a gate electrode (41), a source electrode (10), a drain electrode (12), a second trench (42), and a deep layer (43) of second conductivity types, the base region is provided by the layer (3) of second conductivity types, the source region is provided by the layer (4) of first conductivity type, the gate insulating layer (40 ) is formed p5 a surface of the base region between the source region and the shift of operation, the gate electrode (41) is formed p5 a surface of the gate insulating layer (40), the source electrode (10) is electrically connected to the layer (4) of first conductivity type, the drain electrode (12) is electrically connected to the substrate (1) of first conductivity type, the second trench (42) reaches the operating layer (2) by penetrating the layer (4) of first conductivity type and the layer (3) of second conductivity The deep layer (43) of other conductivity types is buried in the second trench (42), and a source-to-drain current is controlled by controlling a potential of the gate electrode (41).
[10]
The silicon carbide semiconductor device according to claim 9, wherein the first trench (45) and the second trench (42) have the same depth.
[11]
A silicon carbide semiconductor device according to claim 9 or 10, wherein a second trench (6 ') is formed in the transistor cell region (R1) and reaches the operating layer (2) by penetrating the layer (4) of first conductivity type and the layer (3) of second conductivity types, 31 the gate insulating layer (40) and the gate electrode (41) are formed in the second trench (6 ') so that the MOSFET has a trench gate structure, and the second trench (6') of the trench gate structure is deeper than the second trench (42). ).
[12]
A method of manufacturing a silicon carbide semiconductor device, the silicon carbide semiconductor device comprising: a semiconductor substrate (5) comprising a substrate (1) of first conductivity type, an operating layer (2) of first conductivity type on the substrate (1) of first conductivity type, a layer (3) of second conductivity type on the operating layer (2), and a layer (4) of first conductivity type on the layer (3) of second conductivity types; a transistor formed in a transistor cell region (R1) of the semiconductor substrate (5); and an outer voltage breakdown resistant structure formed in an outer voltage breakthrough resistant structure region (R2) surrounding an outer periphery of the transistor cell region (R1), the method comprising: a step of manufacturing the semiconductor substrate (5); a step of forming a first trench (13, 45) in the outer voltage breakdown resistant structural region (R2) so that the first trench (13, 45) surrounds the outer periphery of the transistor cell region (R1); a step of forming a buried layer (15, 46) of second conductivity layers in the first ditch (13, 45), and a step of forming a first recess (17) which is deeper than the layer (4) of first conductivity layers and the layer (3) of second conductivity type and when the operating layer (2) on the sacient is set that the first recess (17) surrounds the outer periphery of the transistor cell region (R1), wherein in the step of forming the first recess (17), the first trench ( 13, 45) are arranged at a side surface of the first recess (17) on an inner periphery of the first recess (17) so that the side surface of the first recess (17) is provided by the buried layer (15, 46) of other conductivity types. father to form an electrically field relieving structure having the buried layer (15, 46) of other conductivity types.
[13]
The method of claim 12, further comprising: a step of forming a second recess (16) deeper than a thickness of the layer (4) of first conductivity type such that the second recess (16) surrounds the outer periphery of the transistor cell region ( R1), wherein in the step of forming the first recess (17), the first trench (13, 45) is arranged at a boundary between the first recess (17) and the second recess (16) so that the side surface of the 32 first recess the recess (17) at the boundary between the first recess (17) and the second recess (16) is provided by the buried layer (15, 46) of second conductivity type to form the electrically field relieving structure having the buried layer (15, 46) of other conductivity types.
[14]
The method of claim 13, further comprising: a step of forming a second conductivity layer (18, 19) on an adjacent side of a bottom surface of the second recess (16) to the first recess (17) and on an adjacent side of a bottom surface of the first recess (17) to the second recess (16) in such a way that the second conductivity layer (18, 19) is joined to the buried layer (15, 46) of second conductivity type to form a RESURF layer ( 20) of second conductivity type providing the electrically faut relieving structure, the step of forming the second conductivity layer (18, 19) following the step of forming the first recess (17) and the step of forming the second recess (16), and the step of forming the second conductivity layer (18, 19) comprises a step of aft forming a mask on a surface of the substrate and a step of performing ion implantation of contaminants of other conductivity types in a direction normal to the substrate geno m to use the mask.
[15]
The method of claim 12, wherein in the step of forming the first ditch (13, 45), a plurality of first ditches (13, 45) comprising the first ditch (13, 45) are formed so that the plurality of first ditches (13, 45) is arranged outwardly from the boundary between the first recess (17) and the second recess (16), and in the step of forming the buried layer (15, 46) of other conductivity types, the buried layer (15, 46) is formed. ) of other types of conductivity in each of the plurality of first ditches (13, 45) to form a protective ring structure which provides the electrically field relieving structure.
[16]
A method according to claim 12 or 15, wherein in the step of forming the first ditch (13, 45) a plurality of first ditches (13, 45) comprising the first ditch (13, 45) are formed in such a way that the plurality of the first ditch (13, 45) is arranging food from the boundary between the first recess (17) and the second recess (16), and in the step of forming the buried layer (15, 46) of other conductivity types the buried layer (15) is formed. , 46) of second conductivity types in each of the plurality of 33 first ditches (13, 45) to form a protective ring structure which provides the electrically field relieving structure.
[17]
A method according to claim 15 or 16, wherein in the step of forming the first ditch (13, 45) the plurality of first ditches (13, 45) are formed such that the plurality of first ditches (13, 45) are arranged in descending order of their width in an outward direction of the transistor cell region (R1).
[18]
The method of any of claims 12-17, further comprising: a step of forming a JFET in the transistor cell region (R1), the JFET having a first gate region provided by the layer (3) of other conductivity types and a sourcing region provided by the layer (4) of the first conductivity type, the step of forming the JFET comprising a step of forming a second trench (6) which reaches the operating shift (2) by penetrating the layer (4) of the first conductivity type and the layer (3) of second conductivity type, a step of forming a channel layer (7) of first conductivity type by epitaxial growth on an inner cradle of the second ditch (6), a step of forming a second gate region (8) of second conductivity types on the channel layer (7), a step of forming a source electrode (10) electrically connected to the layer (4) of first conductivity type, and a step of forming a drain electrode (12) electrically connected to the substrate (1) of first conductivity type, and a source -to-drain-current is controlled by controlling a potential of at least one of the first street region (3) and the second street region (8).
[19]
The method of claim 18, further comprising: a step of forming a buried layer (14) of first conductivity type in the first trench (13), the step of forming the buried layer (46) of second conductivity types being performed after the step of forming the buried layer (14) of first conductivity type, the step of forming the first ditch (13) and the step of forming the second ditch (6) are performed at the same time, the step of forming the buried layer (14) of first conductivity type and the step of forming the channel layer (7) are performed at the same time, and the step of forming the buried layer (15) of other conductivity type and the step of forming the second street region (8) are performed at the same time.
[20]
The method of any of claims 12-17, further comprising: a step of forming a MOSFET in the transistor cell region (R1), the MOSFET having a base region provided by the layer (3) of other conductivity types and a source region provided by the layer. (4) of first conductivity type, wherein the step of forming the MOSFET comprises a step of forming a second trench (42) which reaches the operating layer (2) by penetrating the layer (4) of first conductivity type and the layer (3) of second conductivity stroke, a step of forming a deep layer (43) of second conductivity strokes in the second trench (42), a step of forming a gate insulating layer (40) on a surface of the base region between the source region and the operating layer, a step of forming a gate electrode (41) p5 a surface of the gate insulating layer (40), forming a source electrode (10) electrically connected to the layer (4) of first conductivity type, and a step of forming a drain electrode (12) electrically connected to su the first conductivity type substrate (1), and a source-to-drain current is controlled by controlling a potential of the gate electrode (41).
[21]
The method of claim 20, wherein the step of forming the first trench (45) and the step of forming the second trench (42) are performed at the same time, and the step of forming the buried layer (46) of second conductivity strokes and the step of forming the deep layer (43) is performed p5 at the same time.
[22]
The method of claim 20 or 21, further comprising: a step of forming another trench (6 ') in the transistor cell region (R1) p5 so that the second trench (6') is deeper than the second trench (42) and when the operating layer (2) by penetrating the layer (4) of the first conductivity type and the layer (3) of second conductivity types, the gate insulating layer (40) and the gate electrode (41) being formed in the second trench (6 ') so that the MOSFET : en has a dike gate structure. 1/16 FIG. IA BEG RAVD EPITAXIAL REGION R3 TRANSISTOR CELL REGION R1 '(TIRE VOLTAGE BREAKTHROUGH RESISTANCE REGION R2 FIG. 1 11 9 2/16

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法律状态:

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申请号 | 申请日 | 专利标题

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